Development update 03-31-15
vor 2 StundenDetails
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We have been working very hard in the development of ACSMA, our ultra-optimized Scrypt mining architecture; this work is carried out at our ASIC development facility in Denver Colorado USA.
In order to test this very dense logic design several steps have been taken.
Step 1: Test of reduced number of blocs being mined in a simplified version of ACSMA.
This first step required two phases:
A simulation of a simplified version of ACSMA is tested thoroughly on a PC server in order to verify the functioning of the complete mining process, configuration and communications.
The logic Synthesis ,this is the process of converting high level language used to create ACSMA into hardware primitives like gates memory, FIFOs, registers etc. . This is to analyze resources requirement and FPGA verification using an ACHRONIX testbed , for demo purposes.
Step 2: Test of Full version of ACSMA with reduced number of Scrypt defined ROMMIX units (this because of memory requirements).
This second step required two phases:
A simulation of mining process is tested on a PC server. Once again this is to verify the full functioning of the mining process of a large scale ACSMA unit.
The logic Synthesis and FPGA verification is also used to analyze logic resources using a dual XILINX-ACHRONIX testbed.
This also to showcase our product.
The Cadence Palladium III:
Delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification.
It reduce time to results with high throughput (up to 1,000,000X faster than RTL simulation)
We have been working at all these points concurrently. We can show now results of point 1 and point 2.
We have our demo of point 3 is almost ready to show pretty soon.
Once point 4 is finished and shown, ASIC preparation can start with our ASIC partner.
So we will keep you posted as we are excited about all this taking shape now.
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